239 lines
24 KiB
BibTeX
239 lines
24 KiB
BibTeX
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@inproceedings{auerbach_compiler_2012,
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address = {San Francisco California},
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title = {A compiler and runtime for heterogeneous computing},
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isbn = {978-1-4503-1199-1},
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url = {https://dl.acm.org/doi/10.1145/2228360.2228411},
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doi = {10.1145/2228360.2228411},
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abstract = {Heterogeneous systems show a lot of promise for extracting highperformance by combining the benefits of conventional architectures with specialized accelerators in the form of graphics processors (GPUs) and reconfigurable hardware (FPGAs). Extracting this performance often entails programming in disparate languages and models, making it hard for a programmer to work equally well on all aspects of an application. Further, relatively little attention is paid to co-execution—the problem of orchestrating program execution using multiple distinct computational elements that work seamlessly together.},
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language = {en},
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urldate = {2024-07-16},
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booktitle = {Proceedings of the 49th {Annual} {Design} {Automation} {Conference}},
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publisher = {ACM},
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author = {Auerbach, Joshua and Bacon, David F. and Burcea, Ioana and Cheng, Perry and Fink, Stephen J. and Rabbah, Rodric and Shukla, Sunil},
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month = jun,
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year = {2012},
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pages = {271--276},
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file = {Auerbach et al. - 2012 - A compiler and runtime for heterogeneous computing.pdf:/home/ricardo/Zotero/storage/LCRKBKYC/Auerbach et al. - 2012 - A compiler and runtime for heterogeneous computing.pdf:application/pdf},
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}
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@article{y_y_2014,
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title = {异构并行编程模型研究与进展},
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volume = {25},
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issn = {1000-9825},
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url = {https://kns.cnki.net/kcms2/article/abstract?v=Dm4VI7mKrXMfvAZUNMUgX8reCA9i2gYJadV_oeNwrIXov3W3N3cznGwXoHcCBEa4U5IUycTU9RRAyeLGki8bNkCldPuZc4yQ0E68KW7fvo9-mj97g39uJA==&uniplatform=NZKPT&language=gb},
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doi = {10.13328/j.cnki.jos.004608},
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abstract = {近年来,异构系统硬件飞速发展.为了解决相应的编程和执行效率问题,异构并行编程模型已被广泛使用和研究.从异构并行编程接口与编译/运行时支持系统两个角度总结了异构并行编程模型最新的研究成果,它们为异构架构和上层应用带来的技术挑战提供了相应的解决方案.最后,结合目前的研究现状以及异构系统的发展,提出了异构并行编程模型的未来方向.},
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language = {中文;},
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number = {7},
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journal = {软件学报},
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author = {刘, 颖 and 吕, 方 and 王, 蕾 and 陈, 莉 and 崔, 慧敏 and 冯, 晓兵},
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year = {2014},
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keywords = {GPU, 异构并行编程模型, 异构系统, 编程接口, 编译, 运行时系统},
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pages = {1459--1475},
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file = {异构并行编程模型研究与进展_刘颖:/home/ricardo/Zotero/storage/GJDAISVR/异构并行编程模型研究与进展_刘颖.pdf:application/pdf},
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}
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@article{cai_coala_2024,
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title = {{COALA}: {A} {Compiler}-{Assisted} {Adaptive} {Library} {Routines} {Allocation} {Framework} for {Heterogeneous} {Systems}},
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volume = {73},
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copyright = {https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html},
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issn = {0018-9340, 1557-9956, 2326-3814},
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shorttitle = {{COALA}},
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url = {https://ieeexplore.ieee.org/document/10495065/},
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doi = {10.1109/TC.2024.3385269},
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language = {en},
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number = {7},
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urldate = {2024-10-14},
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journal = {IEEE Transactions on Computers},
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author = {Cai, Qinyun and Tan, Guanghua and Yang, Wangdong and He, Xianhao and Yan, Yuwei and Li, Keqin and Li, Kenli},
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month = jul,
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year = {2024},
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pages = {1724--1737},
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file = {PDF:/home/ricardo/Zotero/storage/LVBVKYIS/Cai et al. - 2024 - COALA A Compiler-Assisted Adaptive Library Routines Allocation Framework for Heterogeneous Systems.pdf:application/pdf},
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}
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@article{dubach_compiling_nodate,
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title = {Compiling a high-level language for {GPUs}: (via language support for architectures and compilers)},
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abstract = {Languages such as OpenCL and CUDA offer a standard interface for general-purpose programming of GPUs. However, with these languages, programmers must explicitly manage numerous lowlevel details involving communication and synchronization. This burden makes programming GPUs difficult and error-prone, rendering these powerful devices inaccessible to most programmers.},
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language = {en},
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author = {Dubach, Christophe and Cheng, Perry and Rabbah, Rodric and Bacon, David F and Fink, Stephen J},
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file = {PDF:/home/ricardo/Zotero/storage/NXNGV5KB/Dubach et al. - Compiling a high-level language for GPUs (via language support for architectures and compilers).pdf:application/pdf},
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}
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@article{auerbach_lime_nodate,
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title = {Lime: a {Java}-compatible and synthesizable language for heterogeneous architectures},
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abstract = {The halt in clock frequency scaling has forced architects and language designers to look elsewhere for continued improvements in performance. We believe that extracting maximum performance will require compilation to highly heterogeneous architectures that include reconfigurable hardware.},
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language = {en},
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author = {Auerbach, Joshua and Bacon, David F and Cheng, Perry and Rabbah, Rodric},
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file = {PDF:/home/ricardo/Zotero/storage/F7TKF8C2/Auerbach et al. - Lime a Java-compatible and synthesizable language for heterogeneous architectures.pdf:application/pdf},
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}
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@article{besard_effective_2019,
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title = {Effective {Extensible} {Programming}: {Unleashing} {Julia} on {GPUs}},
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volume = {30},
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copyright = {https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html},
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issn = {1045-9219, 1558-2183, 2161-9883},
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shorttitle = {Effective {Extensible} {Programming}},
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url = {https://ieeexplore.ieee.org/document/8471188/},
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doi = {10.1109/TPDS.2018.2872064},
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abstract = {GPUs and other accelerators are popular devices for accelerating compute-intensive, parallelizable applications. However, programming these devices is a difficult task. Writing efficient device code is challenging, and is typically done in a low-level programming language. High-level languages are rarely supported, or do not integrate with the rest of the high-level language ecosystem. To overcome this, we propose compiler infrastructure to efficiently add support for new hardware or environments to an existing programming language. We evaluate our approach by adding support for NVIDIA GPUs to the Julia programming language. By integrating with the existing compiler, we significantly lower the cost to implement and maintain the new compiler, and facilitate reuse of existing application code. Moreover, use of the high-level Julia programming language enables new and dynamic approaches for GPU programming. This greatly improves programmer productivity, while maintaining application performance similar to that of the official NVIDIA CUDA toolkit.},
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language = {en},
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number = {4},
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urldate = {2024-10-20},
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journal = {IEEE Transactions on Parallel and Distributed Systems},
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author = {Besard, Tim and Foket, Christophe and De Sutter, Bjorn},
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month = apr,
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year = {2019},
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pages = {827--841},
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file = {PDF:/home/ricardo/Zotero/storage/7VH3HSRD/Besard et al. - 2019 - Effective Extensible Programming Unleashing Julia on GPUs.pdf:application/pdf},
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}
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@article{faingnaert_flexible_2022,
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title = {Flexible {Performant} {GEMM} {Kernels} on {GPUs}},
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volume = {33},
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copyright = {https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html},
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issn = {1045-9219, 1558-2183, 2161-9883},
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url = {https://ieeexplore.ieee.org/document/9655458/},
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doi = {10.1109/TPDS.2021.3136457},
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abstract = {General Matrix Multiplication or GEMM kernels take centre place in high performance computing and machine learning. Recent NVIDIA GPUs include GEMM accelerators, such as NVIDIA’s Tensor Cores. Their exploitation is hampered by the twolanguage problem: it requires either low-level programming which implies low programmer productivity or using libraries that only offer a limited set of components. Because rephrasing algorithms in terms of established components often introduces overhead, the libraries’ lack of flexibility limits the freedom to explore new algorithms. Researchers using GEMMs can hence not enjoy programming productivity, high performance, and research flexibility at once. In this paper we solve this problem. We present three sets of abstractions and interfaces to program GEMMs within the scientific Julia programming language. The interfaces and abstractions are co-designed for researchers’ needs and Julia’s features to achieve sufficient separation of concerns and flexibility to easily extend basic GEMMs in many different ways without paying a performance price. Comparing our GEMMs to state-of-the-art libraries cuBLAS and CUTLASS, we demonstrate that our performance is in the same ballpark of the libraries, and in some cases even exceeds it, without having to write a single line of code in CUDA C++ or assembly, and without facing flexibility limitations.},
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language = {en},
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number = {9},
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urldate = {2024-10-20},
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journal = {IEEE Transactions on Parallel and Distributed Systems},
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author = {Faingnaert, Thomas and Besard, Tim and De Sutter, Bjorn},
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month = sep,
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year = {2022},
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pages = {2230--2248},
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file = {PDF:/home/ricardo/Zotero/storage/JUHZTABS/Faingnaert et al. - 2022 - Flexible Performant GEMM Kernels on GPUs.pdf:application/pdf},
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}
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@inproceedings{tiotto_experiences_2024,
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address = {Edinburgh, United Kingdom},
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title = {Experiences {Building} an {MLIR}-{Based} {SYCL} {Compiler}},
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copyright = {https://doi.org/10.15223/policy-029},
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isbn = {9798350395099},
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url = {https://ieeexplore.ieee.org/document/10444866/},
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doi = {10.1109/CGO57630.2024.10444866},
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abstract = {Similar to other programming models, compilers for SYCL, the open programming model for heterogeneous computing based on C++, would benefit from access to higher-level intermediate representations. The loss of high-level structure and semantics caused by premature lowering to low-level intermediate representations and the inability to reason about host and device code simultaneously present major challenges for SYCL compilers. The MLIR compiler framework, through its dialect mechanism, allows to model domain-specific, high-level intermediate representations and provides the necessary facilities to address these challenges.},
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language = {en},
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urldate = {2024-10-29},
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booktitle = {2024 {IEEE}/{ACM} {International} {Symposium} on {Code} {Generation} and {Optimization} ({CGO})},
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publisher = {IEEE},
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author = {Tiotto, Ettore and Pérez, Víctor and Tsang, Whitney and Sommer, Lukas and Oppermann, Julian and Lomüller, Victor and Goli, Mehdi and Brodman, James},
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month = mar,
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year = {2024},
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pages = {399--410},
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file = {PDF:/home/ricardo/Zotero/storage/LJBFS32J/Tiotto et al. - 2024 - Experiences Building an MLIR-Based SYCL Compiler.pdf:application/pdf},
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}
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@article{perez_user-driven_2023,
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title = {User-driven {Online} {Kernel} {Fusion} for {SYCL}},
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volume = {20},
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issn = {1544-3566, 1544-3973},
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url = {https://dl.acm.org/doi/10.1145/3571284},
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doi = {10.1145/3571284},
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abstract = {Heterogeneous programming models are becoming increasingly popular to support the ever-evolving hardware architectures, especially for new and emerging specialized accelerators optimizing specific tasks. While such programs provide performance portability of the existing applications across various heterogeneous architectures to some extent, short-running device kernels can affect an application performance due to overheads of data transfer, synchronization, and kernel launch. While in applications with one or two short-running kernels the overhead can be negligible, it can be noticeable when these short-running kernels dominate the overall number of kernels in an application, as it is the case in graph-based neural network models, where there are several small memory-bound nodes alongside few large compute-bound nodes.
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To reduce the overhead, combining several kernels into a single, more optimized kernel is an active area of research. However, this task can be time-consuming and error-prone given the huge set of potential combinations. This can push programmers to seek a tradeoff between (a) task-specific kernels with low overhead but hard to maintain and (b) smaller modular kernels with higher overhead but easier to maintain. While there are DSL-based approaches, such as those provided for machine learning frameworks, which offer the possibility of such a fusion, they are limited to a particular domain and exploit specific knowledge of that domain and, as a consequence, are hard to port elsewhere. This study explores the feasibility of a user-driven
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kernel fusion
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through an extension to the SYCL API to address the automation of kernel fusion. The proposed solution requires programmers to define the subgraph regions that are potentially suitable for fusion without any modification to the kernel code or the function signature. We evaluate the performance benefit of our approach on common neural networks and study the performance improvement in detail.},
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language = {en},
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number = {2},
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urldate = {2024-10-29},
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journal = {ACM Transactions on Architecture and Code Optimization},
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author = {Pérez, Víctor and Sommer, Lukas and Lomüller, Victor and Narasimhan, Kumudha and Goli, Mehdi},
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month = jun,
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year = {2023},
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pages = {1--25},
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file = {PDF:/home/ricardo/Zotero/storage/MRYW3TTN/Pérez et al. - 2023 - User-driven Online Kernel Fusion for SYCL.pdf:application/pdf},
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}
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@incollection{hutchison_accull_2012,
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address = {Berlin, Heidelberg},
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title = {{accULL}: {An} {OpenACC} {Implementation} with {CUDA} and {OpenCL} {Support}},
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volume = {7484},
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isbn = {978-3-642-32819-0 978-3-642-32820-6},
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shorttitle = {{accULL}},
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url = {http://link.springer.com/10.1007/978-3-642-32820-6_86},
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abstract = {The irruption in the HPC scene of hardware accelerators, like GPUs, has made available unprecedented performance to developers. However, even expert developers may not be ready to exploit the new complex processor hierarchies. We need to find a way to leverage the programming effort in these devices at programming language level, otherwise, developers will spend most of their time focusing on device-specific code instead of implementing algorithmic enhancements. The recent advent of the OpenACC standard for heterogeneous computing represents an effort in this direction. This initiative, combined with future releases of the OpenMP standard, will converge into a fully heterogeneous framework that will cope the programming requirements of future computer architectures. In this work we present accULL, a novel implementation of the OpenACC standard, based on the combination of a source to source compiler and a runtime library. To our knowledge, our approach is the first providing support for both OpenCL and CUDA platforms under this new standard.},
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language = {en},
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urldate = {2024-11-06},
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booktitle = {Euro-{Par} 2012 {Parallel} {Processing}},
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publisher = {Springer Berlin Heidelberg},
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author = {Reyes, Ruymán and López-Rodríguez, Iván and Fumero, Juan J. and De Sande, Francisco},
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editor = {Hutchison, David and Kanade, Takeo and Kittler, Josef and Kleinberg, Jon M. and Mattern, Friedemann and Mitchell, John C. and Naor, Moni and Nierstrasz, Oscar and Pandu Rangan, C. and Steffen, Bernhard and Sudan, Madhu and Terzopoulos, Demetri and Tygar, Doug and Vardi, Moshe Y. and Weikum, Gerhard and Kaklamanis, Christos and Papatheodorou, Theodore and Spirakis, Paul G.},
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year = {2012},
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doi = {10.1007/978-3-642-32820-6_86},
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note = {Series Title: Lecture Notes in Computer Science},
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pages = {871--882},
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file = {PDF:/home/ricardo/Zotero/storage/I3TR6EWF/Reyes et al. - 2012 - accULL An OpenACC Implementation with CUDA and OpenCL Support.pdf:application/pdf},
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}
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@incollection{malawski_sycl-bench_2020,
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address = {Cham},
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title = {{SYCL}-{Bench}: {A} {Versatile} {Cross}-{Platform} {Benchmark} {Suite} for {Heterogeneous} {Computing}},
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volume = {12247},
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isbn = {978-3-030-57674-5 978-3-030-57675-2},
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shorttitle = {{SYCL}-{Bench}},
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url = {https://link.springer.com/10.1007/978-3-030-57675-2_39},
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abstract = {The SYCL standard promises to enable high productivity in heterogeneous programming of a broad range of parallel devices, including multicore CPUs, GPUs, and FPGAs. Its modern and expressive C++ API design, as well as flexible task graph execution model give rise to ample optimization opportunities at run-time, such as the overlapping of data transfers and kernel execution. However, it is not clear which of the existing SYCL implementations perform such scheduling optimizations, and to what extent. Furthermore, SYCL’s high level of abstraction may raise concerns about sacrificing performance for ease of use. Benchmarks are required to accurately assess the performance behavior of high-level programming models such as SYCL. To this end, we present SYCLBench, a versatile benchmark suite for device characterization and runtime benchmarking, written in SYCL. We experimentally demonstrate the effectiveness of SYCL-Bench by performing device characterization of the NVIDIA TITAN X GPU, and by evaluating the efficiency of the hipSYCL and ComputeCpp SYCL implementations.},
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language = {en},
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urldate = {2024-11-11},
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booktitle = {Euro-{Par} 2020: {Parallel} {Processing}},
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publisher = {Springer International Publishing},
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author = {Lal, Sohan and Alpay, Aksel and Salzmann, Philip and Cosenza, Biagio and Hirsch, Alexander and Stawinoga, Nicolai and Thoman, Peter and Fahringer, Thomas and Heuveline, Vincent},
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editor = {Malawski, Maciej and Rzadca, Krzysztof},
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year = {2020},
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doi = {10.1007/978-3-030-57675-2_39},
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note = {Series Title: Lecture Notes in Computer Science},
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pages = {629--644},
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file = {PDF:/home/ricardo/Zotero/storage/7YQEHBJJ/Lal et al. - 2020 - SYCL-Bench A Versatile Cross-Platform Benchmark Suite for Heterogeneous Computing.pdf:application/pdf},
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}
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@inproceedings{dagli_shared_2024,
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address = {Edinburgh United Kingdom},
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title = {Shared {Memory}-contention-aware {Concurrent} {DNN} {Execution} for {Diversely} {Heterogeneous} {System}-on-{Chips}},
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isbn = {9798400704352},
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url = {https://dl.acm.org/doi/10.1145/3627535.3638502},
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doi = {10.1145/3627535.3638502},
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abstract = {Two distinguishing features of state-of-the-art mobile and autonomous systems are: 1) There are often multiple workloads, mainly deep neural network (DNN) inference, running concurrently and continuously. 2) They operate on shared memory System-on-Chips (SoC) that embed heterogeneous accelerators tailored for specific operations. State-of-the-art systems lack efficient performance and resource management techniques necessary to either maximize total system throughput or minimize end-to-end workload latency. In this work, we propose HaX-CoNN, a novel scheme that characterizes and maps layers in concurrently executing DNN inference workloads to a diverse set of accelerators within an SoC. Our scheme uniquely takes per-layer execution characteristics, shared memory (SM) contention, and inter-accelerator transitions into account to find optimal schedules. We evaluate HaX-CoNN on NVIDIA Orin, NVIDIA Xavier, and Qualcomm Snapdragon 865 SoCs. Our experimental results indicate that HaX-CoNN can minimize memory contention by up to 45\% and improve total latency and throughput by up to 32\% and 29\%, respectively, compared to the state-of-the-art.},
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language = {en},
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urldate = {2024-11-18},
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booktitle = {Proceedings of the 29th {ACM} {SIGPLAN} {Annual} {Symposium} on {Principles} and {Practice} of {Parallel} {Programming}},
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publisher = {ACM},
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author = {Dagli, Ismet and Belviranli, Mehmet E.},
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month = mar,
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year = {2024},
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pages = {243--256},
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file = {PDF:/home/ricardo/Zotero/storage/4UPZN9QQ/Dagli and Belviranli - 2024 - Shared Memory-contention-aware Concurrent DNN Execution for Diversely Heterogeneous System-on-Chips.pdf:application/pdf},
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}
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@article{zhou_deeptm_2024,
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title = {{DeepTM}: {Efficient} {Tensor} {Management} in {Heterogeneous} {Memory} for {DNN} {Training}},
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volume = {35},
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copyright = {https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html},
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issn = {1045-9219, 1558-2183, 2161-9883},
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shorttitle = {{DeepTM}},
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url = {https://ieeexplore.ieee.org/document/10606082/},
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doi = {10.1109/TPDS.2024.3431910},
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abstract = {Deep Neural Networks (DNNs) have gained widespread adoption in diverse fields, including image classification, object detection, and natural language processing. However, training large-scale DNN models often encounters significant memory bottlenecks, which ask for efficient management of extensive tensors. Heterogeneous memory system, which combines persistent memory (PM) modules with traditional DRAM, offers an economically viable solution to address tensor management challenges during DNN training. However, existing memory management methods on heterogeneous memory systems often lead to low PM access efficiency, low bandwidth utilization, and incomplete analysis of model characteristics. To overcome these hurdles, we introduce an efficient tensor management approach, DeepTM, tailored for heterogeneous memory to alleviate memory bottlenecks during DNN training. DeepTM employs page-level tensor aggregation to enhance PM read and write performance and executes contiguous page migration to increase memory bandwidth. Through an analysis of tensor access patterns and model characteristics, we quantify the overall performance and transform the performance optimization problem into the framework of Integer Linear Programming. Additionally, we achieve tensor heat recognition by dynamically adjusting the weights of four key tensor characteristics and develop a global optimization strategy using Deep Reinforcement Learning. To validate the efficacy of our approach, we implement and evaluate DeepTM, utilizing the TensorFlow framework running on a PMbased heterogeneous memory system. The experimental results demonstrate that DeepTM achieves performance improvements of up to 36\% and 49\% compared to the current state-of-the-art memory management strategies AutoTM and Sentinel, respectively.},
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language = {en},
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number = {11},
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urldate = {2024-11-18},
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journal = {IEEE Transactions on Parallel and Distributed Systems},
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author = {Zhou, Haoran and Rang, Wei and Chen, Hongyang and Zhou, Xiaobo and Cheng, Dazhao},
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month = nov,
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year = {2024},
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pages = {1920--1935},
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file = {PDF:/home/ricardo/Zotero/storage/QFNGXW66/Zhou et al. - 2024 - DeepTM Efficient Tensor Management in Heterogeneous Memory for DNN Training.pdf:application/pdf},
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}
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@article{yao_memory-constraint-aware_nodate,
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title = {A {Memory}-{Constraint}-{Aware} {List} {Scheduling} {Algorithm} for {Memory}-{Constraint} {Heterogeneous} {Muti}-{Processor} {System}},
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abstract = {An effective scheduling algorithm is vital for the execution efficiency of applications on Heterogeneous Muti-Processor System (HMPS), especially Memory-Constraint Heterogeneous Muti-Processor System (MCHMPS). Stringent local and external memory constraints have significant impact on the execution performance of applications executed on MCHMPS, predictability is also a critical factor for task scheduling on MCHMPS. Therefore, a novel list scheduling algorithm termed Memory-constraint-aware Improved Predict Priority and Optimistic Processor Selection Scheduling (MIPPOSS), essentially a heuristic search optimization algorithm, is proposed in this paper. In MIPPOSS, a predictive approach is applied for task prioritization and processor selection, and a novel memory-constraint-aware approach is employed in the processor selection phase. MIPPOSS has polynomial complexity and produces better results for application scheduling on target architecture. Randomly generated DAGs and 3 real-world applications experiments, including Cybershake, LIGO, and Montage, show that MIPPOSS outperforms the other five competing algorithms by a large margin.},
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language = {en},
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author = {Yao, Yu and Song, Yukun and Huang, Ying and Ni, Wei and Zhang, Duoli},
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file = {PDF:/home/ricardo/Zotero/storage/7UL7SXWV/Yao et al. - A Memory-Constraint-Aware List Scheduling Algorithm for Memory-Constraint Heterogeneous Muti-Process.pdf:application/pdf},
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}
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