diff --git a/YaeBlog/source/drafts/hpc-2025-heterogeneous-quantum-computing.md b/YaeBlog/source/drafts/hpc-2025-heterogeneous-quantum-computing.md deleted file mode 100644 index 16c255e..0000000 --- a/YaeBlog/source/drafts/hpc-2025-heterogeneous-quantum-computing.md +++ /dev/null @@ -1,10 +0,0 @@ ---- -title: High Performance Computing 25 SP Quantum Computing -date: 2025-06-12T19:26:24.6668760+08:00 -tags: - - 高性能计算 - - 学习资料 ---- - - - diff --git a/YaeBlog/source/drafts/hpc-2025-non-stored-program-computing/image-20250815093113115.png b/YaeBlog/source/drafts/hpc-2025-non-stored-program-computing/image-20250815093113115.png deleted file mode 100644 index 71b6cad..0000000 --- a/YaeBlog/source/drafts/hpc-2025-non-stored-program-computing/image-20250815093113115.png +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:b53da6b4cccca74178369af383fbf3c01d2906d660a5b61158858d9c83be98a0 -size 77370 diff --git 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a/YaeBlog/source/drafts/hpc-2025-cuda.md b/YaeBlog/source/posts/hpc-2025-cuda.md similarity index 99% rename from YaeBlog/source/drafts/hpc-2025-cuda.md rename to YaeBlog/source/posts/hpc-2025-cuda.md index 6032782..bf76da6 100644 --- a/YaeBlog/source/drafts/hpc-2025-cuda.md +++ b/YaeBlog/source/posts/hpc-2025-cuda.md @@ -1,12 +1,13 @@ --- title: High Performance Computing 25 SP NVIDIA -date: 2025-04-24T19:02:36.1077330+08:00 +date: 2025-08-31T13:50:42.8639950+08:00 tags: - 高性能计算 - 学习资料 --- + Fxxk you, NVIDIA! diff --git a/YaeBlog/source/drafts/hpc-2025-cuda/image-20250424192311202.webp b/YaeBlog/source/posts/hpc-2025-cuda/image-20250424192311202.webp similarity index 100% rename from YaeBlog/source/drafts/hpc-2025-cuda/image-20250424192311202.webp rename to YaeBlog/source/posts/hpc-2025-cuda/image-20250424192311202.webp diff --git a/YaeBlog/source/drafts/hpc-2025-cuda/image-20250424192825010.webp b/YaeBlog/source/posts/hpc-2025-cuda/image-20250424192825010.webp similarity index 100% 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ASICs is also called as **Cell-based ASIC(CBIC)**. -![image-20250815093113115](./hpc-2025-non-stored-program-computing/image-20250815093113115.png) +![image-20250815093113115](./hpc-2025-non-stored-program-computing/image-20250815093113115.webp) > The *gate* is used a unit to measure the ability of semiconductor to store logical elements. @@ -84,7 +86,7 @@ Depending on the structure, the standard PLD can be divided into: - Programmable Logic Array(PLA): A programmable array of AND gates feeding a programmable of OR gates. - Complex Programmable Logic Device(CPLD) and Field Programmable Gate Array(FPGA): complex enough to be called as *architecture*. -![image-20250817183832472](./hpc-2025-non-stored-program-computing/image-20250817183832472.png) +![image-20250817183832472](./hpc-2025-non-stored-program-computing/image-20250817183832472.webp) @@ -96,7 +98,7 @@ Depending on the structure, the standard PLD can be divided into: ### FPGA Architecture -![image-20250817184419856](./hpc-2025-non-stored-program-computing/image-20250817184419856.png) +![image-20250817184419856](./hpc-2025-non-stored-program-computing/image-20250817184419856.webp) #### Configurable Logic Block(CLB) Architecture @@ -116,7 +118,7 @@ LUT is a ram with data width of 1 bit and the content is programmed at power up. The below figure shows LUT working: -![image-20250817185111521](./hpc-2025-non-stored-program-computing/image-20250817185111521.png) +![image-20250817185111521](./hpc-2025-non-stored-program-computing/image-20250817185111521.webp) The configuration memory holds the output of truth table entries, so that when the FPGA is restarting it will run with the same *program*. @@ -126,7 +128,7 @@ And as the truth table entries are just bits, the program of FPGA is called as * Let the input signal as address, the LUT will be configured as a RAM. Normally, LUT mode performs read operations, the address decoders can generate clock signal to latches for writing operation. -![image-20250817185859510](./hpc-2025-non-stored-program-computing/image-20250817185859510.png) +![image-20250817185859510](./hpc-2025-non-stored-program-computing/image-20250817185859510.webp) #### Routing Architecture @@ -134,7 +136,7 @@ The logic blocks are connected to each though programmable routing network. And Horizontal and vertical mesh or wire segments interconnection by programmable switches called programmable interconnect points(PIPs). -![image-20250817192006784](./hpc-2025-non-stored-program-computing/image-20250817192006784.png) +![image-20250817192006784](./hpc-2025-non-stored-program-computing/image-20250817192006784.webp) These PIPs are implemented using a transmission gate controlled by a memory bits from the configuration memory. @@ -146,7 +148,7 @@ Several types of PIPs are used in the FPGA: - Non-decoded MUX: n wire segments each with a configuration bit. - Compound cross-point: 6 breakpoint PIPs and can isolate two isolated signal nets. -![image-20250817194355228](./hpc-2025-non-stored-program-computing/image-20250817194355228.png) +![image-20250817194355228](./hpc-2025-non-stored-program-computing/image-20250817194355228.webp) #### Input/Output Architecture @@ -158,7 +160,7 @@ The programmable Input/Output cells consists of three parts: - Routing resources. - Programmable I/O voltage and current levels. -![image-20250817195139631](./hpc-2025-non-stored-program-computing/image-20250817195139631.png) +![image-20250817195139631](./hpc-2025-non-stored-program-computing/image-20250817195139631.webp) #### Fine-grained and Coarse-grained Architecture @@ -186,9 +188,9 @@ Three types of interconnected devices have been commonly used to connect there w ### FPGA Design Flow -![image-20250817195714935](./hpc-2025-non-stored-program-computing/image-20250817195714935.png) +![image-20250817195714935](./hpc-2025-non-stored-program-computing/image-20250817195714935.webp) -![image-20250817200350750](./hpc-2025-non-stored-program-computing/image-20250817200350750.png) +![image-20250817200350750](./hpc-2025-non-stored-program-computing/image-20250817200350750.webp) The FPGA configuration techniques contains: @@ -222,7 +224,7 @@ The OpenCL is not an traditional hardare description language. And OpenCL needs The follow figure shows how the OpenCL-FPGA compiler turns an vector adding function into the circuit. -![image-20250829210329225](./hpc-2025-non-stored-program-computing/image-20250829210329225.png) +![image-20250829210329225](./hpc-2025-non-stored-program-computing/image-20250829210329225.webp) The compiler generates three stages for this function: diff --git a/YaeBlog/source/drafts/hpc-2025-non-stored-program-computing/image-20250605185212740.webp b/YaeBlog/source/posts/hpc-2025-non-stored-program-computing/image-20250605185212740.webp similarity index 100% rename from YaeBlog/source/drafts/hpc-2025-non-stored-program-computing/image-20250605185212740.webp rename to YaeBlog/source/posts/hpc-2025-non-stored-program-computing/image-20250605185212740.webp diff --git a/YaeBlog/source/drafts/hpc-2025-non-stored-program-computing/image-20250612184120333.webp b/YaeBlog/source/posts/hpc-2025-non-stored-program-computing/image-20250612184120333.webp similarity index 100% rename from YaeBlog/source/drafts/hpc-2025-non-stored-program-computing/image-20250612184120333.webp rename to YaeBlog/source/posts/hpc-2025-non-stored-program-computing/image-20250612184120333.webp diff --git a/YaeBlog/source/posts/hpc-2025-non-stored-program-computing/image-20250815093113115.webp b/YaeBlog/source/posts/hpc-2025-non-stored-program-computing/image-20250815093113115.webp new file mode 100644 index 0000000..e6096da --- /dev/null +++ b/YaeBlog/source/posts/hpc-2025-non-stored-program-computing/image-20250815093113115.webp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:319b14c97406e1136c65698092690ea5aaaf6c0daaffc3396b0c41c3503da48b +size 24062 diff --git a/YaeBlog/source/posts/hpc-2025-non-stored-program-computing/image-20250817183832472.webp b/YaeBlog/source/posts/hpc-2025-non-stored-program-computing/image-20250817183832472.webp new file mode 100644 index 0000000..6fd531a --- /dev/null +++ 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a/YaeBlog/source/drafts/hpc-2025-opencl.md +++ b/YaeBlog/source/posts/hpc-2025-opencl.md @@ -1,11 +1,12 @@ --- -title: High Performance Computing 2025 SP OpenCL Programming -date: 2025-05-29T18:29:14.8444660+08:00 +title: High Performance Computing 25 SP OpenCL Programming +date: 2025-08-31T13:51:02.0181970+08:00 tags: - 高性能计算 - 学习资料 --- + Open Computing Language. diff --git a/YaeBlog/source/drafts/hpc-2025-opencl/image-20250529185915068.webp b/YaeBlog/source/posts/hpc-2025-opencl/image-20250529185915068.webp similarity index 100% rename from YaeBlog/source/drafts/hpc-2025-opencl/image-20250529185915068.webp rename to YaeBlog/source/posts/hpc-2025-opencl/image-20250529185915068.webp diff --git a/YaeBlog/source/drafts/hpc-2025-opencl/image-20250529191215424.webp b/YaeBlog/source/posts/hpc-2025-opencl/image-20250529191215424.webp similarity index 100% rename from YaeBlog/source/drafts/hpc-2025-opencl/image-20250529191215424.webp rename to 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diff --git a/YaeBlog/source/drafts/hpc-2025-potpourri/image-20250612191035632.webp b/YaeBlog/source/posts/hpc-2025-potpourri/image-20250612191035632.webp similarity index 100% rename from YaeBlog/source/drafts/hpc-2025-potpourri/image-20250612191035632.webp rename to YaeBlog/source/posts/hpc-2025-potpourri/image-20250612191035632.webp diff --git a/YaeBlog/source/drafts/hpc-2025-potpourri/image-20250612191118473.webp b/YaeBlog/source/posts/hpc-2025-potpourri/image-20250612191118473.webp similarity index 100% rename from YaeBlog/source/drafts/hpc-2025-potpourri/image-20250612191118473.webp rename to YaeBlog/source/posts/hpc-2025-potpourri/image-20250612191118473.webp diff --git a/YaeBlog/source/drafts/hpc-2025-program-cuda.md b/YaeBlog/source/posts/hpc-2025-program-cuda.md similarity index 88% rename from YaeBlog/source/drafts/hpc-2025-program-cuda.md rename to YaeBlog/source/posts/hpc-2025-program-cuda.md index aa19aea..e4ff6b7 100644 --- a/YaeBlog/source/drafts/hpc-2025-program-cuda.md +++ b/YaeBlog/source/posts/hpc-2025-program-cuda.md @@ -1,11 +1,12 @@ --- -title: High Performance Computing 2025 SP Programming CUDA -date: 2025-05-15T19:13:48.8893010+08:00 +title: High Performance Computing 25 SP Programming CUDA +date: 2025-08-31T13:50:53.6891520+08:00 tags: - 高性能计算 - 学习资料 --- + Compute Unified Device Architecture diff --git a/YaeBlog/source/drafts/hpc-2025-program-cuda/image-20250515195739382.webp b/YaeBlog/source/posts/hpc-2025-program-cuda/image-20250515195739382.webp similarity index 100% rename from YaeBlog/source/drafts/hpc-2025-program-cuda/image-20250515195739382.webp rename to YaeBlog/source/posts/hpc-2025-program-cuda/image-20250515195739382.webp diff --git a/YaeBlog/source/drafts/hpc-2025-program-cuda/image-20250515195907764.webp b/YaeBlog/source/posts/hpc-2025-program-cuda/image-20250515195907764.webp similarity index 100% rename from YaeBlog/source/drafts/hpc-2025-program-cuda/image-20250515195907764.webp rename to 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