feat: hpc notebooks
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title: High Performance Computing 25 SP Quantum Computing
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date: 2025-06-12T19:26:24.6668760+08:00
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tags:
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- 高性能计算
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- 学习资料
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---
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<!--more-->
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title: High Performance Computing 25 SP NVIDIA
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date: 2025-04-24T19:02:36.1077330+08:00
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date: 2025-08-31T13:50:42.8639950+08:00
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tags:
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- 高性能计算
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- 学习资料
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---
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Fxxk you, NVIDIA!
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<!--more-->
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---
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title: High Performance Computing 2025 SP Non Stored Program Computing
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date: 2025-05-29T18:29:28.6155560+08:00
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title: High Performance Computing 25 SP Non Stored Program Computing
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date: 2025-08-31T13:51:17.5260660+08:00
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tags:
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- 高性能计算
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- 学习资料
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---
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No Von Neumann Machines.
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<!--more-->
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@@ -60,7 +62,7 @@ There are two types of semi-custom ASICs:
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The Standard cell based ASICs is also called as **Cell-based ASIC(CBIC)**.
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> The *gate* is used a unit to measure the ability of semiconductor to store logical elements.
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@@ -84,7 +86,7 @@ Depending on the structure, the standard PLD can be divided into:
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- Programmable Logic Array(PLA): A programmable array of AND gates feeding a programmable of OR gates.
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- Complex Programmable Logic Device(CPLD) and Field Programmable Gate Array(FPGA): complex enough to be called as *architecture*.
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@@ -96,7 +98,7 @@ Depending on the structure, the standard PLD can be divided into:
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### FPGA Architecture
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#### Configurable Logic Block(CLB) Architecture
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@@ -116,7 +118,7 @@ LUT is a ram with data width of 1 bit and the content is programmed at power up.
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The below figure shows LUT working:
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The configuration memory holds the output of truth table entries, so that when the FPGA is restarting it will run with the same *program*.
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@@ -126,7 +128,7 @@ And as the truth table entries are just bits, the program of FPGA is called as *
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Let the input signal as address, the LUT will be configured as a RAM. Normally, LUT mode performs read operations, the address decoders can generate clock signal to latches for writing operation.
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#### Routing Architecture
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@@ -134,7 +136,7 @@ The logic blocks are connected to each though programmable routing network. And
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Horizontal and vertical mesh or wire segments interconnection by programmable switches called programmable interconnect points(PIPs).
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These PIPs are implemented using a transmission gate controlled by a memory bits from the configuration memory.
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@@ -146,7 +148,7 @@ Several types of PIPs are used in the FPGA:
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- Non-decoded MUX: n wire segments each with a configuration bit.
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- Compound cross-point: 6 breakpoint PIPs and can isolate two isolated signal nets.
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#### Input/Output Architecture
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@@ -158,7 +160,7 @@ The programmable Input/Output cells consists of three parts:
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- Routing resources.
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- Programmable I/O voltage and current levels.
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#### Fine-grained and Coarse-grained Architecture
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@@ -186,9 +188,9 @@ Three types of interconnected devices have been commonly used to connect there w
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### FPGA Design Flow
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The FPGA configuration techniques contains:
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@@ -222,7 +224,7 @@ The OpenCL is not an traditional hardare description language. And OpenCL needs
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The follow figure shows how the OpenCL-FPGA compiler turns an vector adding function into the circuit.
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The compiler generates three stages for this function:
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---
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title: High Performance Computing 2025 SP OpenCL Programming
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date: 2025-05-29T18:29:14.8444660+08:00
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title: High Performance Computing 25 SP OpenCL Programming
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date: 2025-08-31T13:51:02.0181970+08:00
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tags:
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- 高性能计算
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- 学习资料
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---
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Open Computing Language.
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<!--more-->
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@@ -1,11 +1,12 @@
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---
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title: High Performance Computing 25 SP Potpourri
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date: 2025-06-12T18:45:49.2698190+08:00
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date: 2025-08-31T13:51:29.8809980+08:00
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tags:
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- 高性能计算
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- 学习资料
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---
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Potpourri has a good taste.
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<!--more-->
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@@ -1,11 +1,12 @@
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---
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title: High Performance Computing 2025 SP Programming CUDA
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date: 2025-05-15T19:13:48.8893010+08:00
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title: High Performance Computing 25 SP Programming CUDA
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date: 2025-08-31T13:50:53.6891520+08:00
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tags:
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- 高性能计算
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- 学习资料
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---
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Compute Unified Device Architecture
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<!--more-->
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